TWO-CHANNEL ANALOG-TO-DIGITAL CONVERTER USING “URAL-10” MODULES

A. V. Trikhanov, A. N. Osokin, T. G. Grigorieva

(Presented by the scientific seminar of the Department of Computer Engineering)

For a system of digital recording on magnetic tape and input into a digital computer of continuous electrical signals [4], a two-channel analog-to-digital converter (ADC) using “Ural-10” modules, operating on the principle of bit-by-bit balancing, was developed, manufactured, and tested. The functional diagram of the converter is shown in Fig. 1. Flip-flops T1–T8 constitute an eight-bit code register; one-shots Ov1–Ov8 are the pulse distributor; coincidence circuits 1, 3, ..., 15 are the output gates of the ADC.

Fig. 1. Functional diagram of a two-channel ADC.

The differentiating stages DK1–DK8 are intended for setting the register flip-flops to the one state, and coincidence circuits 2, 4, ..., 16 to the zero state. The inverse value of the code from the register is fed to the digital-to-analog converter (DAC), which is in the feedback loop of the ADC. Depending on the position of switch P, the feedback is closed through comparison circuit CC1 when operating on the first channel, through comparison circuit CC2 on the second channel, and in turn through both comparison circuits when operating in the two-channel version.

The input voltages \(U_{\text{in}}1\) and \(U_{\text{in}}2\), respectively, are applied to comparison circuits 1 and 2. Connection of the outputs of the comparison circuits into the reset circuit of the register flip-flops is carried out by means of flip-flop T9, coincidence circuits 17, 18, and summing circuit 9.

Fig. 2. Schematic diagram of the comparison circuit.

On the “Start” signal, the channels are switched, the code is issued, the register is reset in common, and the distributor is started. On the leading edge of the pulse from the single-shot multivibrator, a differentiating stage is triggered; the signal from its output switches the register flip-flop to the one state. The register code is converted into the feedback voltage \(U_{\text{fb}}\). If \(U_{\text{fb}} > U_{\text{in}}\), then the comparison circuit is triggered, and the signal from its output, through the coincidence circuit opened by pulse \(O_{\text{B}}\), is applied to the zero input of the register flip-flop. The common reset signal and the reset signals from the output of the comparison circuit are combined by summing circuits 1–8. In a similar way, the elements of all eight bits of the ADC operate sequentially. The necessary delays of the “Start” signal are provided by delay elements \(D1\), \(D2\).

As is known [1], a bit-by-bit balancing converter is characterized by increased speed; however, it requires a high-speed comparison circuit. For the given ADC functional circuit, the operating frequency of the comparison circuit \(f\) can be determined by the following formula:

\[ f = 2n \cdot f_k \frac{T_k}{T_{\text{P}}} = \frac{2n}{T_{\text{P}}}, \]

where

\(f_k\) and \(T_k\) are the quantization frequency and period, respectively,

\(n\) is the number of bits of the converter,
\(T_{\mathrm{p}}\) is the conversion time.

The coefficient 2 takes into account the double operation of the comparison circuit when processing one bit of the code.

In the ADC circuit, a method of switching analog signals has been applied which provides increased accuracy but has been little studied; it is based on replacing this switching by switching the control signals (signals from the outputs of the comparison circuits installed in all channels) [1, 3].

Fig. 3. Schematic diagram of one bit of the converter.

Such a switching method leads to a lengthening of the feedback path and, consequently, to an increase in the delay of the comparison signal, which requires a certain additional increase in the speed of operation of the comparison circuit. In addition, the presence of several comparison circuits makes it difficult to match the load of the DAC and the comparison circuits and, consequently, leads to un-

...which results in a reduction in the accuracy of the ADC. Nevertheless, the switching method under consideration is characterized by increased accuracy.

The schematic diagram of the DAC is analogous to the circuit in [2]; the difference consists in replacing obsolete semiconductor devices and radio components with modern ones. The comparison circuit is shown in Fig. 2. Since, with this switching method, the DAC is loaded by two comparison circuits, composite transistors PP1–PP4 of the KT312B type are used in the input differential stage. The use of silicon transistors and stabilization of the emitter current by means of transistor PP3 and diodes D3, D4 reduces the temperature drift of the operating threshold, while the use of tunnel diodes D1, D2 in the collector circuit of the input differential stage increases the speed of the circuit. Variable resistor R1 serves for the circuits that equalize the currents through the tunnel diodes. Transistor PP6 in the output stage must have a current gain coefficient \(\beta\) exceeding 65.

To eliminate operation of the composite transistor of the comparison circuit of the switched-off channel in the “open-base” mode, and also to prevent its triggering, a reference voltage \(U_{\text{op}}\), slightly exceeding the maximum input voltage of the converter, is applied to the input of this channel.

The comparison circuit can operate in the input-voltage range \((0 \div 3.5)\ \text{V}\) with a sensitivity of no worse than \(7\ \text{mV}\) at frequencies not exceeding \(800\ \text{kHz}\). The schematic diagrams of one digit of the converter and of the control cell, implemented on “Ural-10” modules, are shown in Figs. 3 and 4, respectively.

The technical characteristics of the ADC are as follows:

1) ranges of DC input voltages — \((0 \div 3.5)\ \text{V}\);

2) output-code word length — 8;

Fig. 4. Schematic diagram of the control cell.

3) conversion time — 32 μsec;
4) sampling frequency — 30 kHz;
5) conversion error in the single-channel version — 0.5%,
in the two-channel version — 0.6%.

In the future, the authors intend to improve these characteristics, in particular, to reduce the conversion time and error by a factor of 2.

REFERENCES

1. E. I. Gitis. Information Converters for Electronic Digital Computing Devices. Moscow, “Energiya,” 1970.

2. G. Ya. Voloshin. Analog-to-digital converter for inputting speech signals into an analog computer. In: Computing Systems. Issue 10, Novosibirsk, 1964.

3. A. V. Trikhanov, A. N. Osokin. Multichannel analog-to-digital conversion. Izvestiya TPI, vol. 266, Tomsk, 1976.

4. A. V. Trikhanov, A. N. Osokin, P. P. Grigor’ev. On the calculation of the magnetic-tape storage unit of a digital recording system. Izvestiya TPI, vol. 266, Tomsk, 1976.