Design of a Unified Set of Blocks for a Given Class of Functional Circuits of Computing Devices

DESIGN OF A UNIFIED SET OF BLOCKS FOR A GIVEN CLASS OF FUNCTIONAL CIRCUITS OF COMPUTING DEVICES

V. K. Pogrebnoy, S. Z. Yampolsky

(Presented by the scientific-technical seminar of the Department of Automated Control Systems and the Control Laboratory)

The traditional approach to solving the problem of arranging the elements of functional circuits of computing devices into blocks, when the principal quality criterion is the minimum total number of interblock connections, is often insufficient, since the use of this criterion in the development of a complex computing device or a series of devices leads to the appearance of a large number of block types. The reason lies in the fact that the design engineer, when solving the arrangement problem, is not in a position to take into account the entire variety of requirements imposed on the solution of this problem and at the same time to analyze the applicability of already existing types of blocks, the number of which continuously grows in the course of design. The rapid growth in the number of block types lengthens the already considerable development time of devices, increases the cost of the device at the design stage and especially during its production. Consequently, questions of block unification in the design of computing devices acquire exceptionally important significance.

The use of standard block types, or of block types already available at the time of design, not only makes it possible to substantially shorten design times and improve the economic indicators of the device, but also to improve significantly its technical indicators. These primarily include reliability, controllability, reduction in the size of the spare-parts and tools set, and a number of others.

Until now, due attention has not been paid to questions of block unification in the design of computing devices. Unification in constructive implementation was limited to the selection of standard designs of blocks, panels, and cabinets, taking into account the possibilities of the technology. In this, as a rule, no scientific approach was used. The problem of unifying blocks by functional purpose, even under specified restrictions on the parameters of a block, is associated with considerable difficulties of both a theoretical and a practical nature. Here, investigations into the fundamental possibility of block unification acquire great importance under conditions where their dimensions are specified and an element base with a definite level of integration is used. It should be noted that with the transition to large integrated circuits the problem of unification is not eliminated. In this case it is considered twice: at the first stage as applied to large-

large-scale integrated circuits (modules), and, at the second level, to blocks.

In studying possible ways of solving the problem of block unification, two main directions may be distinguished. The first consists in analyzing the totality of functional circuits of computing devices that reflect the characteristics of a certain class of devices, and in designing a unified set of standard blocks suitable for implementing circuits of this class. The second consists in analyzing the available set of nonstandard blocks in order to determine the possibility of using them to implement a circuit. This approach is used when there is no set of standard blocks, or when such blocks have low applicability in implementing a particular circuit. Thus, the two approaches complement one another and, in order to achieve a higher level of unification, must be used jointly. The present paper considers questions related to the design of a unified set of blocks.

The problems of designing a unified set of blocks (USB) may be considered in two aspects, which follow from the presence of specific constraints on the structural parameters of blocks. Under conditions in which the parameters of a block are specified rigidly, the level of unification depends mainly on the methods and algorithms used in designing the USB. Here it is understood that the choice of such parameters is made without taking into account the requirements imposed by unification. Another formulation of the problem is also possible, in which the values of the upper and lower bounds for variation of the block parameters are specified. These values are chosen with allowance for the capabilities of technology, reliability, ease of assembly, and other factors. In this case, when designing the USB, it is possible to vary the block parameters within the prescribed range and, by comparing the economic indices of unification with the economic indices of other factors, to find the optimal solution.

In the present paper the problem of designing a USB is considered for rigidly specified block parameters. However, this does not mean that solving the problem in the second formulation will require the development of fundamentally new methods, since designing a USB for fixed values of the block parameters from a prescribed range is no different from solving the problem in the first formulation. In addition, it is necessary only to develop a procedure for evaluating the USB variants obtained for different fixed values of the block parameters and for selecting the optimal variant among them. One of the basic requirements that a USB must satisfy is high applicability of the blocks of the set in implementing circuits of computing devices of the prescribed class. The class of functional circuits is determined by the series of logic elements on which the circuits are developed, by the commonality of the principles of organization and functional purpose of the computing devices, and also by the list of standard units and their various circuit implementations (modifications) used in developing the circuits.

In terms of mathematical statistics, the prescribed class of circuits is a population \(L\), in which the number of circuits is assumed to be very large. By the time work begins on composing modules into blocks, there is a specific set of circuits belonging to this class. Thus, there is a certain sample \(\sigma\) from the population \(L\). When the circuits of this sample are analyzed, sample characteristics are obtained which, with a certain probability depending on the size of the sample \(\sigma\), can be extended to the population-

ness \(L\). If the sample is small, then the sample characteristics do not reflect, with sufficient probability, even the most essential characteristics of the population \(L\). A UCB constructed on the basis of characteristics obtained from a small sample, even if very effective methods are available, will reflect the characteristics only of that particular sample. Therefore, the applicability of the blocks of such a UCB for implementing circuits not belonging to the sample will be low. In this case, when new circuits appear, it is necessary to adjust the UCB.

When designing a number of computing complexes or a series of computing devices, it is possible to analyze a representative sample of circuits from a given class. In particular, all circuits of one computing complex may be taken as such a sample. Such a sample is characterized by the fact that it most fully reflects the varieties of functional circuits of the given class and their quantitative ratio. The result of analyzing the sample of circuits is a list of logically connected sets of modules, with an indication of the frequencies of their use in the analyzed circuits of the sample. Depending on the parameters of a block, one or several sets of modules may be included in it. It is assumed here that the sets are included autonomously.

A unified set of blocks must contain a minimal number of block types and, at the same time, have minimal redundancy when implementing the next circuit of the given class. Obviously, these requirements are contradictory. Therefore, it becomes necessary to determine the optimal size of the set of blocks. In doing so, both technical and economic indicators must be taken into account. When forming the blocks of the set, it is also necessary that they be filled with modules to the maximum extent. With a limited number of connector contacts, the quality of filling the blocks depends on the sizes of the logically connected sets from which the blocks are formed. As the number of modules in the sets increases, the quality of filling the blocks improves. At the same time, sets of small size will occur more often in the circuits; therefore, striving to use only large sets leads to a reduction in the level of unification. To achieve the maximum possible level of unification in this case, it is necessary to increase the number of contacts in the block connector.

In accordance with the above requirements, the problem of designing a UCB is formulated as follows. It is necessary to carry out a structural analysis of a sample of functional circuits of computing devices in order to identify in them frequently recurring logically connected sets of modules (hereinafter referred to as typical structures), and to distribute the resulting list of typical structures among blocks in such combinations that would subsequently make it possible to implement the functional circuits of the given class by means of the blocks of the set with minimal redundancy.

The development and study of methods for designing a unified set of blocks leads to the necessity of solving a number of problems, which may be combined into the following main groups:

1) structural analysis of functional circuits;
2) formation of the blocks of the unified set;
3) determination of the optimal size of the unified set.

To carry out structural analysis, the functional circuit is interpreted as a directed graph \(G = (P, U)\). The vertices \(p_i\) of the graph \(G\) are the logical elements of the circuit or more complex logical

structures if they contain non-interchangeable groups of inputs [1]. All inputs within such groups are interchangeable. If necessary, the outputs of a logical element may also be divided into groups.

An arc \(p_i \Gamma p_j\) of the graph characterizes the presence of a logical connection (output—input) between elements with ordinal numbers \(p_i\) and \(p_j\). A vertex of the graph \(p_i\) is characterized by the type \(v_i\), by the numbers of the input groups \(\varphi_i\) and output groups \(z_i\). To each arc \(p_i \Gamma p_j \in U\) there corresponds a connection function

\[ \psi_{ij}=f(v_i,\ z_i;\ v_j,\ \varphi_j). \tag{1} \]

The graph \(G=(P,U)\) of the circuit being analyzed is specified by a list of connections \(p_i \Gamma p_j \in U\), with indication of the connection function \(\psi_{ij}\) and the semidegrees of departure \(\alpha(p_i)\) and arrival \(\beta(p_j)\) of the corresponding connection vertices. The graph \(\alpha G'=(P',U')\) of the standard structure is specified analogously.

In solving problems of structural analysis, the problem of graph identification is considered. Here the more important and more difficult problem is that of identical embedding of graphs. It is known that the solution of such problems is associated with a large number of trials, which, as the number of vertices \(n\) in the graph increases, grows so rapidly that even for comparatively small \(n\) it exceeds the capabilities of modern computers [2]. For the circuits under consideration, the graph \(G\) contains hundreds of vertices, and therefore complete enumeration is not feasible. However, a number of features of the graphs under consideration (the number of arcs is comparable with the number of vertices; a great variety of vertex types and group numbers, values of the semidegrees of departure and arrival of vertices) help reduce the number of trials and make it possible to construct quite effective algorithms for solving graph-identification problems in structural analysis of circuits.

The structural analysis of the investigated sample of circuits is carried out in three stages. At the first stage, certainly known standard structures (SS)—standard nodes of digital devices in various modifications—are identified in the circuits.

At the second stage, logically connected elements not included in standard nodes are analyzed, in order to determine sets of modules, characteristic for the sample being analyzed and logically connected, which will subsequently be called stable combinations.

The third stage consists in identifying stable combinations among the elements not included in standard nodes.

The process of identifying the graph \(G'=(P',U')\) (the standard structure) in the graph \(G=(P,U)\) (the functional circuit) consists in the successive checking of arcs of the graphs \(G'\) and \(G\) under the conditions of identity and equivalent completion. Two arcs \(p_i \Gamma p_j \in U\) and \(p_m \Gamma p_n \in U'\) are identical if the following conditions hold:

\[ \begin{aligned} \text{a)}\quad & \psi_{ij}=\psi_{mn};\\ \text{b)}\quad & \alpha(p_m)\leq \alpha(p_i),\quad \beta(p_m)\leq \beta(p_i);\\ \text{c)}\quad & \alpha(p_n)\leq \alpha(p_j),\quad \beta(p_n)\leq \beta(p_j). \end{aligned} \tag{2} \]

The arc \(p_i^{k+1}\Gamma p_j^{k+1}\) is an equivalent completion to the arc \(p_i^k\Gamma p_j^k\), with respect to the corresponding arcs \(p_m^{k+1}\Gamma p_n^{k+1}\) and \(p_m^k\Gamma p_n^k\) of the graph \(G'\), if the following conditions are satisfied:

\[ \text{a)}\quad p_i^k=p_j^{k+1}\quad \text{when}\quad p_m^k=p_n^{k+1}; \]

\[ \begin{aligned} \text{b)}\quad & p_j^k = p_i^{k+1} \quad \text{when} \quad p_m^k = p_m^{k+1};\\ \text{c)}\quad & p_j^k = p_i^{k+1} \quad \text{when} \quad p_n^k = p_m^{k+1};\\ \text{d)}\quad & p_j^k = p_j^{k+1} \quad \text{when} \quad p_n^k = p_n^{k+1}. \end{aligned} \tag{3} \]

Here \(k = 1, 2 \ldots, h\) are the ordinal numbers of the arcs of the sequence in which they are selected in the graphs \(G'\) and \(G\).

The algorithm for selecting the graph \(G'\) is constructed in such a way that, preliminarily, an arc satisfying condition (2) for some \(k\)-th (initial) arc of the graph \(G'\) is selected in the graph \(G\). After this, a check is made as to whether the graph \(G\) contains a subgraph with the selected arc that is identical to the graph \(G'\). Such a check is carried out by successively attaching to the initial arc arcs of the graph \(G'\), with a simultaneous search, for each of them, for an arc in the graph \(G\) satisfying conditions (2), (3). If such a graph is found, then its arcs are recorded, and in the graph \(G\) a second arc satisfying condition (2) for the initial arc of the graph \(G'\) is selected, and the above-mentioned check for the presence of a subgraph is carried out. If the subgraph is not selected, then the selection process continues in the same way as in the case of its selection.

If, in the process of selecting arcs of the graph \(G'\) in the graph \(G\), it is not possible to reach the last, \(h\)-th, arc, then a so-called backtracking step is made: the arc of the graph \(G\) selected at the preceding step is excluded from consideration, another one is sought in its place, and an attempt is made to reach the \(h\)-th arc through the newly selected arc. The search continues until all arcs of the graph \(G\) that satisfy condition (2) for the initial arc of the graph \(G'\) have been examined. This means that the graph \(G\) does not contain a subgraph with an arc satisfying condition (2) for the initial arc of the graph \(G'\), identical to the graph \(G'\).

The partial subgraph \(G^0 = (P^0, U^0)\), obtained after the selection in the graph of nonintersecting subgraphs of typical structures, is analyzed in order to identify in it the entire set of connected subgraphs \(G_i^f\) (the index \(f\) indicates that the \(i\)-th subgraph contains \(f\) arcs) and to partition it into groups of identical graphs. On the basis of the results, a list of stable combinations is determined and they are selected in the partial subgraphs of all circuits of the sample by the TS-selection algorithm.

Stable combinations whose frequency of use in the analyzed sample of circuits exceeds some established number are accepted as TS and, together with the previously selected TS (typical nodes of digital devices), form the basis for designing a USS.

The problem of forming the blocks of the set is considered as the problem of rationally combining several TS into a block, provided that its design parameters are represented by the following data:

\(Q\) — the maximum number of modules that a block may contain;

\(F\) — the maximum number of connector contacts of the block that can be used in wiring the inputs and outputs of the TS included in the block.

Information on the frequency of use of TS in the analyzed sample of circuits can be represented by the matrix \(A = \|a_{si}\|_{\sigma \times \omega}\), where \(\sigma\) is the number of circuits in the analyzed sample, and \(\omega\) is the number of types of TS obtained as a result of structural analysis. The element \(a_{si}\) of the matrix \(A\) characterizes the number of TS of the \(i\)-th type in the \(s\)-th circuit. For each TS the following are also known:

\(q_i\) — the number of elements constituting a TS of the \(i\)-th type;

\(f_i\) — the number of contacts required for wiring the inputs and outputs of a TS of the \(i\)-th type.

The formation of the blocks of the unified set must meet two basic requirements. Each block of the unified set must contain such a combination of TC that occurs frequently in the analyzed sample of circuits. This achieves high applicability of the given block in covering functional circuits and, at the same time, maximum use of the TC contained in it. The second requirement consists in maximum filling of the block with modules. When forming a block from TC, the problem arises of covering the logic elements of the block’s TC by a minimum number of modules.

Let us represent the information about the elements contained in the modules* in the form of a matrix \(A=\|a_{ij}\|_{m\times n}\), where \(m\) is the number of types of elements contained in the modules; \(n\) is the number of types of modules. The element \(a_{ij}\) of matrix \(A\) characterizes the number of elements of the \(i\)-th type in the \(j\)-th module. Introduce the column vector \(B=\{b_1, b_2, \ldots, b_m\}\), whose components \(b_i\) characterize the number of elements of the \(i\)-th type in the circuit of the block under consideration. Define the variable \(x_j\) as the number of modules of the \(j\)-th type needed to cover the elements of the block’s TC.

In the adopted notation, the problem of minimizing the number of modules when covering the elements of a block can be written in the following form:

\[ \min Z=\sum_{j=1}^{n} x_j, \tag{4} \]

subject to

\[ \sum_{j=1}^{n} a_i x_j \geq b_i,\quad i=1,2,\ldots,m; \tag{5} \]

\[ x_j \geq 0,\quad j=1,2,\ldots,n; \tag{6} \]

\[ x_j \text{ is an integer for all } j=1,2,\ldots,n. \tag{7} \]

To solve problem (4)–(7), with preliminary reduction of its dimension, the algorithm proposed in [3] may be used. The value of the objective function \(Z_l^*\), obtained in solving problem (4)–(7) for the \(l\)-th block, must not exceed the value \(Q\).

The quality of filling of the \(l\)-th block after solving problem (4)–(7) is assessed by the filling coefficient \(K_l\), which is determined by the formula

\[ K_l=\frac{Z_l^*}{Q}. \tag{8} \]

To determine combinations of TC that frequently occur in the analyzed sample of circuits, it is necessary to introduce an estimate of the “connectedness” between TC. Given such an estimate, the problem of forming a block is reduced to selecting the most connected set of TC satisfying the constraints on the design parameters of the block.

The connection between TC is estimated by the matrix \(A'=\|a'_{si}\|_{S\times \omega}\), obtained as a result of transforming the matrix \(A\). The transformation process is carried out to “smooth” the peak values of the elements of matrix \(A\), which are not characteristic of the entire sample of circuits, but occur in individual circuits and can be implemented by blocks containing TC of one type. The elements \(a'_{si}\) are determined from the condition

* A certain series of integrated circuits (modules) on which the analyzed circuits are implemented is considered.

\[ 0 \leq a_{si}^{*}=(a_{si}-kh)<h_i, \tag{9} \]

where

\(h_i\) is the maximum number of TC of the \(i\)-th type that can be included in one block,

\(K=1,2,\ldots\) is an integer.

The value \(h_i\) is determined from the conditions:

\[ \text{a) }\quad Z_{h_i}^{*}\leq Q;\qquad \text{b) }\quad h_i\leq \frac{F}{f_i}\ \text{(integer part).} \tag{10} \]

The number of TC of the \(j\)-th type used in each of the sample circuits is a random variable. The values of the \(j\)-th random variable in the sample \(\sigma\) are represented by column \(A_j\) of the matrix \(A'\). It is known that one of the most important indices for estimating the relationship between two random variables is the correlation coefficient \(r_{ij}\) [4]. The presence of correlation between the \(i\)-th and \(j\)-th TC in the present case indicates that the appearance of the \(i\)-th TC in a circuit entails, with some probability, the appearance of the \(j\)-th TC. Such TC are often connected directly by logical links, which can be identified in the process of structural analysis and used in distributing TC among the blocks of the unified set [5]. The correlation coefficients form the matrix \(R=\|r_{ij}\|_{\omega\times\omega}\). Estimating the priority of one pair of TC in comparison with another by correlation coefficients alone is insufficient. We shall show this using as an example data on the frequency of use of two pairs of TC in a sample of five circuits:

\[ \text{a) }\quad \frac{A_i}{A_j}\ \left|\begin{array}{ccccc} 0&1&2&1&1\\ 0&1&2&1&1 \end{array}\right. \qquad \text{b) }\quad \frac{A_i}{A_j}\ \left|\begin{array}{ccccc} 0&3&2&4&3\\ 0&3&2&4&3 \end{array}\right. . \]

For both pairs \(r_{ij}=1\); however, when covering the circuits, a block containing pair (a) will be used five times, whereas a block containing the TC of pair (b) will be used twelve times. Clearly, from this point of view, when forming the blocks preference should be given to pair (b). To compare pairs of TC according to this condition, a matrix of the frequencies of simultaneous use in the sample of circuits of each pair of TC is constructed: \(Q=\|q_{ij}\|_{\omega\times\omega}\). The element \(q_{ij}\) of the matrix \(Q\) is determined by the formula

\[ q_{ij}=\sum_{s=1}^{\sigma} q_{ijs},\qquad q_{ijs}=\min\{a'_{si},\,a'_{sj}\}. \tag{11} \]

From the matrices \(R\) and \(Q\), a weighted matrix \(Z=\|z_{ij}\|_{\omega\times\omega}\) is constructed, defining a unified estimate of the relationship between TC:

\[ r_{ij}=\beta_r r'_{ij}+\beta_q q'_{ij},\qquad \beta_r+\beta_q=1, \tag{12} \]

where

\(r'_{ij}, q'_{ij}\) are elements of the normalized matrices \(R'\) and \(Q'\);

\(\beta_r, \beta_q\) are weight coefficients characterizing the degree of influence of the elements of the matrices \(R'\) and \(Q'\) on the corresponding element of the matrix \(Z\).

To determine the optimal values of the weight coefficients \(\beta_r\) and \(\beta_q\), the function \(K_{\mathrm{u}}=f(\beta_r,\beta_q)\) is analyzed, where \(K_{\mathrm{u}}\) is the utilization coefficient calculated for a set of blocks when covering the circuits of the sample being analyzed. Studies have shown that this function is unimodal; therefore, to find \(\max K_{\mathrm{u}}\), the Kiefer–Johnson method [6] can be used. The coefficients \(\beta_r\) and \(\beta_q\) corresponding to \(\max K_{\mathrm{u}}\) are optimal.

The formation of the blocks of the set is carried out on the basis of the matrix \(Z\) by finding the most connected aggregate of TC \(t\) satisfying the conditions

\[ \text{a) } \quad Z_t^* < Q, \qquad \text{b) } \quad \sum_{i \in t} f_i \le F, \tag{13} \]

where \(Z_t^*\) is the value of the objective function obtained in solving problem (4)–(7) for the aggregate \(t\).

The frequency with which the \(j\)-th TC must occur in the blocks of the set is determined by the formula

\[ \gamma_j = \frac{\gamma \sum_{s=1}^{\sigma} a'_{si}} {\min \sum_{s=1}^{\sigma} a'_{si}} \;(\text{integer part}), \tag{14} \]

where \(\gamma\) is the frequency of use in the blocks of the set of the TC with the minimum frequency of use in the sample of circuits. The value of \(\gamma\) determines the number of blocks in the set. As \(\gamma\) increases, the number of blocks in the set increases.

A set of blocks formed by the method set forth above contains all types of TC and, consequently, is capable of covering any functional circuit of the given class represented by the aggregate of TC singled out in it. At the same time, for a particular set, its own value of the utilization coefficient \(K_{\mathrm{u}}\) is obtained. The value of the coefficient \(K_{\mathrm{u}}\) depends on the number of types of blocks in the set \(H\), on the quality of the solution of the circuit-covering problem, and also on how rational the combinations of TC that form the corresponding blocks turned out to be. If it is assumed that the covering problem has been solved optimally, and that the block-formation algorithm makes it possible to obtain the most rational combinations of TC from the standpoint of the maximum probability of their joint use in covering circuits, then the coefficient \(K_{\mathrm{u}}\) will depend only on the size of the set \(H\).

An increase in the coefficient \(K_{\mathrm{u}}\) can be achieved by increasing the number of types of blocks in the set; that is, the requirements \(\max K_{\mathrm{u}}\) and \(\min H\) are contradictory. This indicates the need to carry out a special study in order to choose a rational number of blocks in the set from both the technical and the economic points of view.

A decrease in the coefficient \(K_{\mathrm{u}}\) and an increase in the number of blocks in the set \(H\) lead to an increase in the economic costs \(Z\) at the stage of designing computing devices, as well as in creating a unified set of blocks. To determine the optimal values of \(K_{\mathrm{u}}\) and \(H\), it is necessary to find the minimum of the function \(Z = f(K_{\mathrm{u}}, H)\). It does not appear possible to obtain an analytic expression for this function. Its experimental construction is possible by determining three functions: \(Z_k = f(K_{\mathrm{u}})\), \(Z_{\mathrm{n}} = f(H)\), \(K_{\mathrm{u}} = f(H)\), where \(Z_k\) denotes additional economic costs arising as a result of the deviation of the coefficient \(K_{\mathrm{u}}\) from unity; \(Z_{\mathrm{n}}\) denotes additional economic costs arising because of an increase in the number of blocks in the set in the process of its creation and use.

The function \(Z_k = f(K_{\mathrm{u}})\) is constructed under the assumption that \(Z_k = f(K_{\mathrm{u}} = 1) = 0\) and is computed for values of \(K_{\mathrm{u}}\) varying in the range from 1 to 0. When constructing the function \(Z_{\mathrm{n}} = f(H)\), only the additional costs arising in the construction of a new block are taken into account. It should be noted that the value of the function \(Z_k\) reflects the absolute

the magnitude of the costs arising when \(K_{\mathrm{u}}\) is reduced, and therefore depends on the total number of blocks in the set used in the computing complex. In this connection, the optimal number of blocks in the set can be found only with respect to some fixed, in terms of volume, number of blocks of the set used to cover the analyzed sample of circuits, since, with a change in this volume, the minimum of the function \(Z\) will shift toward an increase in the value of \(H\).

Fig. 1. 1 — function \(Z_k=f(K_{\mathrm{u}})\); 2 — function
\(Z_{\mathrm{n}}=f(H)\); 3 — function \(K_{\mathrm{n}}=f(H)\); 4 — function
\(Z=f(K_{\mathrm{u}}, H)\)

The function \(K_{\mathrm{u}}=f(H)\) is constructed from experimental data obtained for several variants of the set of blocks with different values of \(H\). The coefficient \(K_{\mathrm{u}}\) is determined for each variant from the results of solving the problem of covering the circuits of the sample \(\sigma\) with the blocks of the corresponding variant.

The construction of the function of total costs \(Z=f(K_{\mathrm{u}}, H)\) from the known functions \(Z_k=f(K_{\mathrm{u}})\), \(Z_{\mathrm{n}}=f(H)\), and \(K_{\mathrm{u}}=f(H)\), obtained in designing a USB for a real computing complex, is shown in Fig. 1.

A set of blocks with \(H_{\mathrm{opt}}=110\), corresponding to the value \(Z_{\min}\), is taken as the unified set.

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