DECODING WITH CONTROL

A. V. TRIKHANOV

(Presented by the scientific seminar of the Department of Computing Technology)

Decoders (DSh) in electronic digital computers are used in the paths for: number addresses, operation codes, and instruction addresses. Errors and malfunctions in the operation of decoders (reading or writing not at the specified address, execution of a different operation) lead to very serious, sometimes irreparable, consequences. Therefore, control of decoders is exceptionally important; even a substantial complication of the circuit of the indicated paths is justified [1].

Errors and malfunctions of DSh are externally manifested in the following way:

1) either, simultaneously with the true signal, one more false signal appears, i.e., two buses are excited;

2) or the true signal does not appear on any of them;

3) or one, but a false, bus is selected.

For effective control of decoders, it is expedient to set two tasks:

Minimum problem

— when one of the malfunctions considered occurs, the DSh circuit must possess the property of complete control, i.e., both false signals and the nonappearance of true signals must be detected.

Maximum problem

— none of the malfunctions listed above should affect the normal operation of the decoder, i.e., in this case the decoder circuit must possess the property of self-correction.

For solving the indicated problems, known circuit methods of decoder control are of interest. Circuit control of decoders is carried out by various methods: using special codes, using technical solutions. In particular, the known duplication method should be regarded as a special case of using special codes: the code at the outputs of the duplicating decoder is the code obtained by the main decoder. The best-known duplication method provides for the use of two code decoders, whose outputs of the same name should be combined in AND circuits or in OR circuits.

In the first case, the majority of false signals will be detected, but the true signal cannot be produced if it does not appear at the output of at least one of the mutually duplicating decoders.

Combining like-named outputs through OR circuits passes all false signals, but the true signal is produced if at least one of the decoders has operated correctly. Consequently, neither of the two duplication methods satisfies the minimum-problem condition.

As for special codes, this checking can be organized in two ways [1—6]:

— by using an encoder of the complete code, fed to the input of the decoder (indirect checking);

— by using an encoder of the check code, fed together with the complete code to the input of the decoder. The common drawback of these methods should be considered the omission of certain errors in the operation of the decoder and an increase in the word-length grid of the machine.

Methods have been developed that do not require introducing redundancy into the machine word. They are based on various technical solutions.

One such method is the method of engineer V. Zlenko [3, 4, 5], which consists in checking for the presence of one and only one excited bus. The checking circuit according to this method has the form shown in Fig. 1.

Fig. 1. V. Zlenko checking circuit

The input buses of the DS are divided into groups of buses corresponding to identical characteristics (weight, number of ones, etc.). The buses of the groups are connected by an assembly; the signals of these circuits control valves, from whose outputs, under the action of the polling signal, pulses are supplied to a summing transformer circuit with input windings \(\omega_1 \div \omega_5\), connected in agreement. Winding \(\omega_6\) is connected in opposition. When the decoder operates correctly, one bus is excited at its output. The polling signal passes through one valve opened by the excited bus and simultaneously through the polling winding. In this case the resulting flux will be equal to zero, and there will be no signal at the output. In the event of any malfunction, except the selection of one, but false, bus, there will be a fault signal at the transformer output.

If one, but false, bus is selected, then there will be no error signal at the transformer output, although it is in fact present. Thus, this checking method does not completely solve the minimum problem.

Decoder checking using the properties of systematic and group codes is known [4]; it solves the minimum problem and, with additional duplication, also the maximum problem.

A combined method is proposed below, using special decision circuits, which completely solves the minimization problem. In the method based on a summing transformer, in one case, when only one bus is excited (a false one), no error signal is produced. If, in this case, the situation in which only one bus is excited is transformed into another, in which two buses are excited, then the summing transformer will issue an error signal. The stated problem of changing the situation is solved by duplicating the decoder and combining the outputs of the same name of the two decoders either on AND circuits or on OR circuits.

Fig. 2. Decoding with control, combined method (variant 1)

Let us consider both variants in all situations during operation of the decoder: for the three types of malfunctions indicated above and during correct operation (for convenience in the further discussion, we shall denote this type of operation by number 4).

Fig. 3. Decoding with control, combined method (variant 2)

The control system for the AND circuit is shown in Fig. 2; for the OR circuit, in Fig. 3.

In these figures, the control block with a summing transformer has the circuit shown in Fig. 1.

Detection of two excited buses can also be carried out by the method proposed in [2].

The operation of the control system is shown in the table. A minus (plus) sign indicates the absence (presence) of an error, an error signal, an error omission, and correction of the output signal of the decoder.

Table

It is evident that, in operating mode No. 4 (no error), the decoder system with the control circuit functions exactly the same way as a system with a single decoder.

In operating mode No. 1 (an additional false bus is excited), the system with the OR circuit operates the same way as a system with a single decoder, while the system with the AND circuit has corrective capability.

For an error of type 2 (no bus is excited), the situation, in comparison with the preceding case, is reversed: the system with the OR circuit has corrective capability.

The most difficult case (operating mode 3) for the circuit shown in Fig. 1 is the same for both systems of the combined method. However, as can be seen from the table, an error signal is generated by either system.

Thus, the proposed combined method solves the minimum problem completely. It is obvious that combining the two systems will have significant corrective capability.

REFERENCES

1. E. S. Arutyunyan, E. R. Piliposyan, A. N. Sagoyan. On one method of circuit-based detection of decoder errors. Problems of Radio Electronics. Computer Engineering Series, issue 6, Moscow, 1968.

2. E. A. Brik, I. N. Alyanakh. Circuit control of decoders and digital units of storage devices. Proceedings of the North-Western Correspondence Polytechnic Institute, No. 1, Leningrad, 1967.

3. E. I. Klyamko. Circuit and test control of automatic digital computing machines. Sov. Radio, 1963.

4. I. D. Putintsev. Hardware control of control digital computing machines. Sov. Radio, 1966.

5. A. M. Sidorov. Methods of control of electronic digital machines. Sov. Radio, 1966.

6. G. N. Ushakova. Hardware control and reliability of specialized electronic digital computing machines. Sov. Radio, 1969.