MODELING OF A DECODER WITH HARDWARE CONTROL ON A GENERAL-PURPOSE DIGITAL COMPUTER

N. P. Baida, V. I. Naplekov, A. D. Cheredov

(Presented by the scientific seminar of the Department of Computer Engineering)

In the development of digital devices (DD) with hardware control (HC), the problem arises of choosing the best HC method from the set of possible ones. To solve this problem, it is expedient to compare various possible control circuits for a particular DD according to the criteria of control efficiency and reliability [1], taking into account cost constraints. The present work considers questions of modeling a DD with HC on a general-purpose digital computer, with the aim of automatically determining quantitative values of the criteria of efficiency and reliability of HC, which make it possible partially to solve the indicated problem.

As the DD under investigation, a known circuit of a binary decoder (DSh) with HC [2] was taken, the functional diagram of which is presented in Fig. 1. The output buses of the DSh are denoted 00, 01, 10, 11, and the two-position code arriving at the DSh inputs is \(\alpha_1, \overline{\alpha}_1, \alpha_2, \overline{\alpha}_2\). Modeling was carried out according to the schematic diagram (Fig. 2), implemented on integrated elements of type L3-3, performing the OR–NOT function, with three inputs.

The output buses of the DSh are represented by the functions:

\[ \begin{aligned} 00 &\;—\; \overline{X_1 \vee X_2},\\ 01 &\;—\; \overline{X}_1 \wedge X_2,\\ 10 &\;—\; X_1 \wedge \overline{X}_2,\\ 11 &\;—\; X_1 \wedge X_2. \end{aligned} \]

The elements of the control circuit are encoded by means of the functions

\[ \overline{X}_1,\quad \overline{X_1 \vee X_2}\quad \text{and}\quad \overline{X_1 \vee X_2 \vee X_3}. \]

Two programs were compiled:

1. A program modeling the correct operation of the system (by system is meant a DSh with HC).

2. A program modeling a failure in the system.

The first program (the flowchart is given in Fig. 3) is intended for checking the correctness of the development of the schematic diagram of the DSh with HC and was compiled according to the method set forth in [3].

In the flowchart shown in Fig. 3, the following designations are introduced:

subroutine “circuit” — a subroutine modeling the passage of a signal in the system;

Fig. 1. Functional diagram of a decoder with HC

Fig. 2. Principal circuit diagram of a decoder with HC

\(n_{\mathrm{oco}}\) — the number of cases in which error signals are absent at the output of the control circuit;

\(N\) — the number of different combinations of input signals;

\(N^*\) — the maximum number of different combinations of input signals.

In the modeling process, all possible combinations of input signals are enumerated and the reaction of the control circuit is analyzed. The appearance of an error signal at the output of the control circuit means that the basic circuit of the system has been implemented incorrectly. In this case, the states of the system elements are printed; their analysis makes it possible to determine the error made in the design.

Fig. 3. Flowchart of the program for checking the schematic diagram of a DSh with AK

Flowchart labels:

• “Formation, from the table, of the matrix of subdiagrams of the circuit”
• \(n_{\mathrm{oco}} := 0;\quad N := 1\)
• “Subdiagram of the circuit”
• “Are there error signals?”
• yes: \(n_{\mathrm{oco}} := n_{\mathrm{oco}} + 1\)
• no: “Print the states of the circuit”
• \(N := N + 1;\quad N \leq N^*\)
• yes: return to “Subdiagram of the circuit”
• no: “Print \(n/N\)”
• “Stop”

The second program is intended for calculating the efficiency and reliability of control. Its flowchart is given in Fig. 4.

The following additional notation is introduced here:

\(m\) — the multiplicity of failures in the system;

\(m^*\) — the maximum multiplicity of failures;

\(n_m\) — the number of failures of multiplicity \(m\) that are detected by control;

\(r\) — operating mode, \(r^* = 3\);

\(r_1\) — mode for assigning failures only in the main circuit;

\(r_2\) — mode for assigning failures only in the control circuit;

\(r_3\) — mode for assigning multiple failures that occur simultaneously in the main and control apparatus.

The effectiveness and reliability of the check is calculated by the method set forth in [4]. The numerical values of the criteria for the effectiveness and reliability of the check are printed out. The total simulation time of the system (for two programs) on the M-220 computer was 6 minutes. The calculated indices of the effectiveness and reliability of the check coincide with the data obtained as a result of statistical tests of the system over 54 hours, not counting the time for assembling the circuit.

Fig. 4. Flowchart of the program for evaluating the effectiveness and reliability of the check

Conclusions

1. A method has been developed for simulating a decoder with hardware checking on a general-purpose digital computer in order to evaluate the effectiveness and reliability of the check.

2. Using the indicated method, it is possible in a short time to calculate the indices of the effectiveness and reliability of various metho-

hardware-control methods for uniform combinational devices and then, by comparing the results obtained, select the optimal control variant.

REFERENCES

1. N. P. Baida. Efficiency and reliability of hardware control of digital devices. Izvestiya TPI, vol. 230, 1972.

2. E. I. Arutyunyan et al. On one method of circuit-based error detection in a decoder. Questions of Radio Electronics. EVT Series, 1968, issue 6.

3. Application of computers to the design of digital devices. Edited by N. Ya. Matyukhin. “Sovetskoe Radio,” Moscow, 1968.

4. N. P. Baida. Determination of the efficiency and reliability of hardware control in the modeling of digital devices on a digital computer. In the present collection.