Electronic Circuits for High-Efficiency Nuclear Spectroscopy

V. A. Avdeev, V. M. Kuznetsov

(Presented by the scientific and technical seminar of the High-Energy Laboratory, Nuclear Physics Research Institute)

The developed set of electronic circuits for nuclear spectroscopy includes a number of counting devices and logic elements with high time resolution.

I. High-Speed Counting Devices

Counting device with chains of tunnel diodes

Known counting devices (triggers) with a chain of tunnel diodes have a number of shortcomings that limit the possibilities of their application. These include stringent requirements on the stability of power supplies and on tolerances for the spread of element parameters, as well as insufficiently high speed, especially at counting factors greater than three. On the other hand, the simplicity of constructing these circuits explains the effort to use them practically.

The shortcomings listed above can, to a certain extent, be eliminated by using in the trigger (Fig. 1) a parallel connection of se-

Fig. 1.

Fig. 2.

of several chains of tunnel diodes [1] ($\mathrm{TD}_1^i \div \mathrm{TD}_n^i$ is the $i$-th chain). The static characteristic of each chain in Fig. 2 has $n$ peaks, and the characteristic of the $i$-th chain is shifted in voltage relative to the characteristic of the $i-1$-st chain by the amount

\[ \Delta E_k=\frac{U_3-U_1}{k}, \tag{1} \]

where $U_1$, $U_3$ are parameters of the volt-ampere characteristic of a tunnel diode,

$K$ is the number of chains in the trigger.

Through the tunnel diodes of the chains a forward current $I_0$ is specified, lying within the limits

\[ I_{2\max}<I_0<I_{1\min}, \tag{2} \]

where $I_{1\min}$, $I_{2\max}$ are parameters of the volt-ampere characteristic of the tunnel diode, taking their spreads into account.

Therefore each chain has $(n+1)$ stable states $A_0^i \div A_n^i$ ($n$ is the number of tunnel diodes in the chain), and the whole system as a whole has $k\cdot n+1$ stable states $A_0^1 \div A_n^k$. The trigger signal is applied to the chains through the input capacitance $C_{\mathrm{in}}$ and the diode switch $D_1 + D_k$, which, effecting static decoupling of the chains, ensures, at the moment when the trigger signal arrives, the difference in the chains’ voltage thresholds necessary for their sequential switching.

In the initial state of the trigger (the state of all chains is $A_0^1$), the voltage threshold of the first chain for the triggering signal $U_{\mathrm{in}}$ is the smallest, since the volt-ampere characteristics of the remaining chains are shifted in voltage relative to the first by the emf $E_i$

\[ E_i=(i-1)\Delta E_k. \tag{3} \]

Therefore, when an input pulse of a certain duration arrives (greater than the switching time of one chain, but less than the switching time of two chains), the tunnel diode of the first chain switches. The trigger passes into the state $A_0^2$. When subsequent pulses arrive, the remaining chains are switched in turn into the state $A_0^i$. After the switching of the $k$-th chain into the $A_0^k$ state, the next cycle of switching of the chains into the states $A_1^i$ will begin, consecutively from the first to the $k$-th chain; then a new cycle of switching into the state $A_2^i$ will begin, and so on. When the trigger switches into the state $A_n^k$, the reset device operates, and the entire

the system returns to the initial state \(A_0^1\). A quantitative analysis of the switching process shows that the optimum values of the amplitudes of the input pulses (for \(K \geqslant 2\)) are determined as

\[ U_{\text{in,opt}} \simeq U_3 - U_1 . \tag{4} \]

In this case the maximum value of the charging current of the input capacitance during the action of the trigger signal is determined by the relation

\[ I_{c \max} \simeq \frac{K+1}{2}\,(I_0 - I_2). \tag{5} \]

The increase in the charging current of the input capacitance with an increase in the number of cells in the trigger determines the improvement in the resolving power of the device. For the conversion factor (modulus) and the resolving time of the trigger when it is started by short pulses, the following relations have been obtained:

\[ K \cdot n \leqslant \frac{1-\delta t_u}{2\delta t_u} \cdot \frac{U_{3\min}-U_{1\max}}{U_{1\max}} \cdot \frac{I_{1\max}}{I_{1\max}-I_{0\min}}, \tag{6} \]

\[ T_{\text{res}} = \frac{(1.5 \div 2)C_{\text{in}}(U_3-U_1)}{K(I_0-I_2)} \left[ 1+(K-1)\frac{C_{\text{td}}}{C_{\text{in}}} - \frac{2K^2 \cdot U_{\text{sw}}}{(K+1)(U_3-U_1)} \right], \tag{7} \]

where \(\delta t_u\) is the relative range of the duration of the input pulses;

\(U_1, U_{1\min}, U_3, U_{3\min}, I_2, I_{1\max}\) are the parameters of the tunnel diodes, taking into account their possible deviations;

\(I_0, I_{0\min}\) is the bias current of the tunnel-diode circuits;

\[ U_{\text{sw ex}} \simeq n \cdot U_{1\max}\cdot \frac{I_{1\max}-I_{0\min}}{I_{1\max}} . \tag{8} \]

A comparative analysis of expressions (6) and (7) with analogous relations for a trigger with one circuit

\[ n \leqslant \frac{1-\delta_{\text{in}}}{1+\delta_{\text{in}}} \cdot \frac{I_{1\max}}{I_{1\max}-I_{0\min}} \cdot \frac{U_{3\min}-U_{1\max}-U_{\text{sw}}}{U_{1\max}}, \tag{9} \]

\[ T_{\text{res}} = \frac{(1.5 \div 2)C_{\text{in}}(U_3-U_1)}{I_0-I_2} \tag{10} \]

Fig. 3.

shows that, with the same tolerances on the circuit parameters and input signals, for permissible values of the recounting modulus an almost twofold gain is obtained. The speed (reduction in the resolution time) of the trigger increases approximately in proportion to the number of chains \(K\). In practice it is expedient to use triggers with two or three chains; a further increase in the number of chains entails a certain complication of the reset device. Figure 3 gives the schematic diagram of a device with two chains of tunnel diodes. The recounting modulus of the circuit can be varied (by changing the threshold of the reset device) from 1 to 6. The resolution time of the trigger is \(\sim 70\) ns.

Recounting device with a trigger for commutation of the reset threshold

Figure 4 gives a block diagram of a recounting device of the storage type with an additional trigger (3) (cycle counters) for commutating the threshold of the reset device (2) [2]. The principle of a storage-type device consists, as is known, in cyclic filling of the storage element (1) up to the threshold level of the reset device (2), with subsequent resetting of the storage element to its initial state when the specified level of accumulated information in it is exceeded. The principal drawback of recounting devices of this type is the limited (low) values of the recounting moduli. For a linear character of accumulation, for the recounting coefficient there is the limitation

Fig. 4.

\[ n \leqslant \frac{1+(\delta A+\delta \Pi)}{2(\delta A+\delta \Pi)}, \tag{1} \]

where \(\delta A, \delta \Pi\) are the relative tolerances on the amplitude of the input signals and on the threshold level of the reset device, respectively.

For an exponential character of accumulation, the analogous limitation has the form

\[ n \leqslant 1+\frac{\ln k'}{\ln\left(1-\frac{2\delta}{k'}\right)-\ln(1-2\delta)}, \tag{2} \]

where \(k'\) is the dynamic range of the amplitudes of the input pulses that vary exponentially in the course of accumulation,

\(\delta\) is the total relative tolerance of the amplitude of the input signal and of the threshold of the reset device.

In practice, for \(\delta=\delta A+\delta \Pi=0.2\) and \(k'=10\), from expressions (1) and (2) for \(n\) we obtain, respectively, the values \(n \leqslant 3\), \(n \leqslant 5.5\). Thus, even in the case of using a nonlinear accumulation process, the permissible values of the recounting moduli remain insufficiently high. Moreover, the realization of an exponential character of accumulation, especially at high values of \(k'\), in practice encounters great difficulties. Among the principal advantages of this recounting method in comparison with others is its high resolving power. This advantage is determined by the fact that the accumulation process can also proceed continuously.

The use, in the device of Fig. 4, of an additional commutation trigger (3) for the threshold of the reset device (2) makes it possible to obtain any conversion coefficients in accordance with the relation

\[ n=\sum_{i=0}^{m} n_i , \tag{3} \]

where \(n_i\) is the conversion coefficient of the accumulator of the \(i\)-th conversion cycle, and \(m\) is the conversion modulus of the commutation trigger.

In the special case when the cycle counter does not change the threshold of the reset device, and consequently also does not change the conversion modulus of the accumulator \(n_i\), the conversion coefficient is determined by the simple product

\[ n=m\cdot n_i . \tag{4} \]

Fig. 5.

The operating principle of the device is explained by the timing diagrams in Fig. 5. The diagrams are given for the special case in which the commutation trigger (cycle counter) has only two stable states, \(A_0\), \(A_1\). The initial state \(A_0\) of the commutation trigger corresponds, in the diagram, to the conversion modulus of the accumulator \(n_0=3\), while the state \(A_1\) of the commutation trigger corresponds to \(n_1=2\). When the first three pulses arrive at the input of the device, the reset device is actuated, the accumulator returns to its initial state, and the cycle counter switches to state \(A_1\). Switching the counter (3) to state \(A_1\) leads to a change in the threshold of the reset device and, consequently, also in the conversion modulus of the accumulator from three to two. Now, when the next two pulses arrive, the reset device is actuated again. The accumulator, the cycle counter, and therefore the entire device return to the initial state. The process then repeats cyclically. The conversion modulus of the entire device for the trigger considered is equal to the sum of the two conversion cycles of the accumulator

\[ n=n_0+n_1=5. \]

It is evident that the total tolerance on the amplitude of the input signals and the spread of the parameters of the circuit elements is determined for the conversion modulus \(n_0\) of the accumulator. The speed of the counting device is determined primarily by the speed of the accumulator and the reset device. The cycle counter may have a speed \(n_{i\min}\) times lower (for the example considered, \(n_{i\min}=n_1=2\)) than the other functional units of the circuit, since the process of changing the threshold proceeds in parallel with the process of filling the accumulator. The method of commutating the threshold of the reset device is used, in particular, to increase the conversion modulus of a trigger with chains of tunnel diodes, Fig. 6 [3].

Fig. 6.

II. A Logic Element of High Time Resolution

At present, a number of fast coincidence circuits of high time resolution are known. Of these, a differential coincidence circuit is of particular interest. It differs fundamentally from all other circuits in that its resolving time can be less than the duration of the pulses being registered. For circuits of other types, the resolving time is determined, as is known, by the duration of the pulses at the inputs of the channels of the selection element and cannot be less than this duration.

The principle, proposed by Z. Beem [4], for constructing a circuit of double coincidences of the differential type was used by us in synthesizing a multichannel differential coincidence circuit. Figure 7 gives the functional diagram of a multichannel coincidence circuit of the differential type. It includes an ordinary AND coincidence circuit and a NOR logic element. The logical functions of both elements are written as

\[ f_1(a_1, a_2, \ldots a_n)=a_1 \cdot a_2 \cdot \ldots a_n, \tag{1} \]

\[ f_2(b_1, b_2, \ldots b_n)=b_1 \vee b_2 \vee \ldots \vee b_n, \tag{2} \]

where \(a_k, b_k\) are binary variables of the inputs of the coincidence circuit and of the NOR element, respectively.

The inputs \(a_1 \div a_{n-1}\) of the AND coincidence circuit are connected through delay lines \(LZ(t_3)\) to the inputs \(b_1 \div b_{n-1}\) of the NOR element; the output of the NOR ...

Fig. 7.

is connected to input \(a_n\) of the coincidence circuit. Input \(b_n\) of the “NOT-OR” element is used as the input of the external “inhibit.” Taking into account that

\[ b_k=a_k(t-t_3), \tag{3} \]

where \(t-t_3\) is an argument indicating the delay of the binary variables of inputs \(b_k\) relative to the variables of inputs \(a_k\), for the logical functions \(f_1(a_1 \ldots a_n)\), \(f_2(b_1 \ldots b_n)\), we obtain the following expressions:

\[ f_2(b_1,\ldots b_n)=a_n=\overline{a_1(t-t_3)} \vee \overline{a_2(t-t_3)} \vee \ldots \vee \overline{a_{n-1}(t-t_3)} \vee \overline{b_n}, \tag{4} \]

\[ f_1(a_1\ldots a_n)=a_1\cdot a_2\ldots a_{n-1}\cdot \left[\overline{a_1(t-t_3)} \vee \overline{a_2(t-t_3)} \vee \ldots \vee \overline{a_{n-1}(t-t_3)} \vee \overline{b_n}\right]. \tag{5} \]

It follows from expression (5) that, when there is temporal coincidence of the input signals \(a_1 \div a_{n-1}\) and no signal at the input of the external “inhibit” \(b_n\), a signal appears at the output of the circuit. If, however, at least one of the input signals \(a_1 \div a_{n-1}\) arrives relative to the signals of the other inputs with a delay greater than \(t_3\), the delay of the lines LZ\((t_3)\), then the signal from the “NOT-OR” element will perform the “inhibit” operation, and at output “C” there will be no signal.

Thus, the time resolution of the circuit is determined by the value of the delay \(t_3\) of the lines LZ\((t_3)\), and not by the duration of the input signals, as in the case of the ordinary circuit.

Figure 3 shows a schematic diagram of triple coincidences with an external “inhibit” channel \((n=4)\), constructed on the principles considered above. The functional element “AND” is implemented on the transistor current switch \(T_1 \div T_4\) [5]. The second transistor current switch \(T_9 \div T_{13}\), together with the coupling transistor \(T_{14}\), performs the “NOT-OR” operation [6]. The coupling transistor \(T_{14}\) serves for potential matching of the levels of the input and output signals of the coincidence circuit “AND” and the “NOT-OR” element. The remaining elements of the circuit form the threshold discriminator-shaper \(T_5 \div T_8\).

The circuit considered makes it possible to register coincidences of more than three input signals; in this case the number of transistors in the input current switches of the “AND” and “NOT-OR” elements is increased to the number of required inputs.

Fig. 8.

Figure 9, a, b shows the dependences of the time resolution of the circuit on the amplitude of the input pulses for two cases: a) the threshold of the “inhibit” channel is higher than the threshold of the coincidence channel; b) the threshold of the “inhibit” channel is lower than the threshold of the coincidence channel. For comparison, the same graphs also show (with a dashed line) the dependence of the time resolution of the same circuit with the “NOT-OR” channel disconnected (an ordinary

Fig. 9.

coincidence circuit). From the form of the curves for the differential coincidence circuit it follows that, beginning with input-signal voltages greater than the threshold of the “inhibit” channel, only a weak dependence of the circuit’s time resolution on the amplitude of the input signals is observed. This property of the differential circuit provides it with broad possibilities of application in cases where small values and high stability of the time resolution are required.

REFERENCES

1. V. A. Avdeev, V. S. Solov’ev. Author’s certificate No. 275137. Bulletin of Inventions and Discoveries, 22 (1970).

2. V. A. Avdeev. Author’s certificate No. 291342. Bulletin of Inventions and Discoveries, 3 (1971).

3. V. A. Avdeev, V. M. Kuznetsov. Pribory i tekhnika eksperimenta, 6, 67 (1970).

4. Z. Bay. Phys. Rev., 83, 242 (1951).

5. V. A. Avdeev, V. M. Kuznetsov. Pribory i tekhnika eksperimenta, 3, 86 (1971).

6. V. A. Avdeev. Author’s certificate No. 311402. Bulletin of Inventions and Discoveries, 24 (1971).